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low cost 225 mhz 16 16 crosspoint switches ad8114/ad8115 rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 461. 31 13 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . features 16 16 high sp eed nonblocking switch array s ad81 14; g = 1 ad81 15; g = 2 serial or parallel programming of switch array serial d a ta out allows dais y-ch aining of multi p le 16 16 arr a ys t o create larger switch arrays high impedance output di sable allows connection of multiple devic e s without loa d ing the output bus for smaller arr a ys se e the ad 8108/ad 8109 ( 8 8 ) or ad81 10/ad8 1 11 (16 8) swit ch arrays complete solut i on buffered input s programmable high impedan c e outputs 16 output amp l ifiers, ad81 14 (g = 1), a d 81 1 5 (g = 2) drives 150 ? loads excellent vi deo performance 25 mhz, 0.1 db gain flatness 0.05%/0.05 di fferential gain/ d ifferentia l ph ase error (r l = 15 0 ?) excellent ac pe rformance ?3 db bandwi d t h: 225 m hz slew rate: 375 v/s low power of 700 mw ( 2 .75 m w per point) low all hostile crosstalk of ?7 0 db @ 5 mhz reset pin allow s disabling of a ll outputs (con nected through a capacitor to g r ou nd prov ides power-on reset capability) 100-le ad lqfp (14 mm 14 m m ) applic ati o ns routing of high speed signals including video ( n tsc, p a l, s, secam, yuv, r g b ) compressed vi deo (mpeg, wa velet) 3-level digital video (h db3) datacomms telecomms general description the ad8114 /ad8115 1 a r e hig h s p eed 16 16 video cr os s p o i n t sw i t c h ma tr i c e s . th ey o f f e r a ?3 d b si gnal ba n d wid t h gr e a t e r t h a n 200 mh z and c h a n ne l swi t c h tim e s o f les s tha n 50 n s wi t h 1 % s e t t l i ng . w i t h ?70 db of cr o sst a l k an d ?90 db is ola t ion (@ 5 mh z), t h e ad8114/ad81 15 a r e us ef u l in ma n y hig h sp ee d a ppl ic a t ion s . the dif f er e n t i a l gai n and dif f er e n t i al phas e o f b e t t e r tha n 0.05 % an d 0.05, r e s p ec ti vel y , alo n g wi t h 0. 1 db func tio n a l block di agram ad8114/ad8115 output buffer g = +1, g = +2 80 80 256 80-bit shift register with 5-bit parallel loading parallel latch decode 16 5:16 decoders 16 clk data in update ce reset 16 inputs a0 data out 16 outputs set individual or reset all outputs to "off" a1 a2 ser/par d0 d1 d2 d3 d4 enabl e/disabl e a3 switch matrix 01070-001 fi g u r e 1 . f l a t n e s s o u t t o 25 mh z while dr i v in g a 75 ? back-t er mina t e d lo ad , mak e t h e ad8114/ad81 15 ideal f o r al l typ e s o f sig n al swi t c h in g. the ad8114 /ad8115 in c l ude 16 indep e n d en t o u t p u t b u f f ers t h a t c a n b e plac e d i n t o a h i g h i m p e dan c e st a t e fo r p a ra l l elin g c r o ssp oi n t o u tput s s o t h at of f ch an n e l s d o not l o a d t h e output b u s. th e ad81 14 has a ga in o f 1, while t h e ad8115 o f f e rs a ga in o f 2. th e y o p era t e on v o l t ag e s u p p lies o f 5 v w h i l e co n s um in g o n l y 70 m a o f i d le c u rr e n t . th e c h a n n e l sw i t c h in g is p e r f o r m e d vi a a s e r i a l dig i t a l con t r o l (w hich can acco m m o d a t e da isy - chaini n g o f s e vera l d e vic e s) o r vi a a p a ra l l el co n t r o l, a l l o w i ng up d a t i ng of an i n d i v i du a l output w i t h out re pro g r a m m i ng t h e e n t i re ar r a y . the ad8114 /ad8115 is p a c kag ed in 100 -lead l q fp p a c k a g e a nd is a v a i l a b l e o v er t h e ext e n d e d i n d u s t r i al t e m p era t ur e ra n g e o f ?40c t o +85c. 1 p a te nt pe nd ing.
ad8114/ad8115 rev. b | page 2 of 32 table of contents ad8114/ad8115 specifications ................................................. 3 timing characteristics (serial) .................................................. 5 timing characteristics (parallel) ............................................... 6 absolute maximum ratings ............................................................ 8 maximum power dissipation ..................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 i/o schematics ................................................................................ 17 theory of operation ...................................................................... 18 applications ................................................................................. 18 power-on reset .......................................................................... 19 gain selection ............................................................................. 19 creating larger crosspoint arrays .......................................... 20 multichannel video ................................................................... 21 crosstalk ...................................................................................... 22 pcb layout ...................................................................................... 25 evaluation board ............................................................................ 29 control the evaluation board from a pc ................................ 30 overshoot of pc printer ports data lines ............................. 30 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31 revision history 9/05 rev. a to rev. b updated format.................................................................. universal change to figure 3 ............................................................................6 change to absolute maximum ratings..........................................8 changes to maximum power dissipation section........................8 updated outline dimensions ........................................................31 changes to ordering guide ...........................................................31 11/01 rev. 0 to rev. a edits to ordering guide...........................................................5 comments added to outline dimensions ...................................26 revision 0: initial version
ad8114/ad8115 rev. b | page 3 of 32 ad8114/ad8115 specifications v s = 5 v, t a = +25c, r l = 1 k?, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance ?3 db bandwidth 200 mv p-p, r l = 150 ? 150/125 225/200 mhz 2 v p-p, r l = 150 ? 100/125 mhz gain flatness 0.1 db, 200 mv p-p, r l = 150 ? 25/40 mhz 0.1 db, 2 v p-p, r l = 150 ? 20/40 mhz propagation delay 2 v p-p, r l = 150 ? 5 ns settling time 0.1%, 2 v step, r l = 150 ? 40 ns slew rate 2 v step, r l = 150 ? 375/450 v/s noise/distortion performance differential gain error ntsc or pal, r l = 1 k? 0.05 % ntsc or pal, r l = 150 ? 0.05 % differential phase error ntsc or pal, r l = 1 k? 0.05 degrees ntsc or pal, r l = 150 ? 0.05 degrees crosstalk, all hostile f = 5 mhz ?70/?64 db f = 10 mhz ?60/?52 db off isolation, input-output f = 10 mhz, r l = 150 ?, one channel ?90 db input voltage noise 0.01 mhz to 50 mhz 16/18 nv/ hz dc performance gain error no load 0.05/0.2 0.08/0.6 % r l = 1 k? 0.05/0.2 % r l = 150 ? 0.2/0.35 % gain matching no load, channel-channel 0.01/0.5 0.04/1 % r l = 1 k? channel-channel 0.01/0.5 % gain temperature coefficient 0.75/1.5 ppm/c output characteristics output impedance dc, enabled 0.2 ? disabled 10 m? output disable capacitance disabled 5 pf output leakage current disabled 1 a output voltage range no load 3.0 3.3 v voltage range i out = 20 ma 2.5 3 v short-circuit current 65 ma input characteristics input offset voltage worst case (all configurations) 3 15 mv temperature coefficient 10 v/c input voltage range no load 3/1.5 3.5 v input capacitance any switch configuration 5 pf input resistance 1 10 m? input bias current per output selected 2 5 a switching characteristics enable on time 60 ns switching time, 2 v step 50% update to 1% settling 50 ns switching transient (glitch) 20/30 mv p-p
ad8114/ad8115 rev. b | page 4 of 32 parameter conditions min typ max unit power supplies supply current avcc, outputs enabled, no load 70/80 ma avcc, outputs disabled 27/30 ma avee, outputs enabled, no load 70/80 ma avee, outputs disabled 27/30 ma dvcc, outputs enabled, no load 16 ma supply voltage range 4.5 to 5.5 v psrr dc 64 80 db f = 100 khz 66 db f = 1 mhz 46 db operating temperature range temperature range operating (still air) ?40 to +85 c ja operating (still air) 40 c/w
ad8114/ad8115 r e v. b | pa ge 5 o f 3 2 timing characteristics (serial) table 2. timin g characteristics p a r a m e t e r s y m b o l m i n t y p m a x u n i t serial data setup time t 1 2 0 n s clk pulse wid t h t 2 1 0 0 n s serial data hold time t 3 2 0 n s clk pulse separ a tion, serial mo de t 4 1 0 0 n s clk to update delay t 5 0 n s update pulse width t 6 5 0 n s clk to data out val i d, serial mode t 7 2 0 0 n s propagation de l a y, update to switch on or off C 5 0 n s data load time, clk = 5 mhz, s e rial mode C 16 s clk, update rise and fall t imes C 1 0 0 n s reset time C 2 0 0 n s table 3. logic levels v ih v il v oh v ol i ih i il i oh i ol reset , ser /par clk, data i n , ce , update reset , ser /par clk, data i n , ce , update data o u t data o u t reset , ser /par clk, data i n , ce , update reset , ser /par clk, data i n , ce , update data o u t data o u t 2.0 v min 0.8 v max 2.7 v min 0.5 v max 20 a max ?400 a min ?400 a max 3.0 ma min load data into serial register on falling edge 1 0 1 0 data in clk 1 = latched 0 = transparen t data out out7 (d4) out7 (d3) out00 (d0) transfer data from serial register to parallel latches during low level t 7 t 1 t 3 t 6 t 2 t 4 t 5 update 01070-002 f i g u re 2. ti ming d i ag r a m, s e ri al m o d e
ad8114/ad8115 r e v. b | pa ge 6 o f 3 2 timing characteristics (parall e l) table 4. timin g characteristics p a r a m e t e r s y m b o l m i n t y p m a x u n i t data setup tim e t 1 2 0 n s clk pulse wid t h t 2 1 0 0 n s data hold time t 3 2 0 n s clk pulse separ a tion t 4 1 0 0 n s clk to update delay t 5 0 n s update pulse width t 6 5 0 n s propagation de l a y, update to switch on or off C 5 0 n s clk, update rise and fall t imes C 1 0 0 n s reset time C 2 0 0 n s table 5. logic levels v ih v il v oh v ol i ih i il i oh i ol reset , ser /par, clk, d0, d1, d2, d3, d4, a0, a1, a2, a3, ce , update reset , ser /par, clk, d0, d1, d2, d3, d4, a0, a1, a2, a3, ce , update data o u t data o u t reset , ser /par, clk, d0, d1, d2, d3, d4, a0, a1, a2, a3, ce , update reset , ser /par, clk, d0, d1, d2, d3, d4, a0, a1, a2, a3, ce , update data out data out 2.0 v min 0.8 v max 2.7 v min 0.5 v max 20 a max ?400 a min ?4 00 a ma x 3.0 ma min 1 0 1 0 d0 ?d3 a0 ?a2 clk 1 = latched update 0 = transparent t 2 t 1 t 5 t 6 t 3 t 4 01070-003 f i g u re 3. ti ming d i ag r a m, p a r a l l e l m o de
ad8114/ad8115 r e v. b | pa ge 7 o f 3 2 table 6. o p era t ion truth ta b l e ce updat e clk data in data o u t reset ser / par operation/comment 1 x x x x x x no change in logic. 0 1 f data i data i- 8 0 1 0 the data on the serial data in line is loaded into serial regi ster. the first bit cl ocked into the serial register appear s at dat a out 80 clocks later. 0 1 f d0d4, a0 a3 na in paralle l m o d e 1 1 the data on the parallel da ta lin e s, d0 to d4, are load ed into the 80 bit serial shift register locatio n addressed by a0 to a3. 0 0 x x x 1 x data in the 80-bit shift register t r ansfers into the parallel latches t h at control the switch array. latches are tran sparent. x x x x x 0 x asynchronous operation. all outputs are disabled. remainder of logic is unchange d. d clk q 4 to 1 6 de code r a0 a1 a2 clk 16 256 data in (serial) (output enable) ser/par ce update out0 en data out parallel data d q clk d q clk d q clk d q clk d1 d2 d3 d q clk d q clk d q clk d q clk d q clk out1 en out2 en out3 en out4 en out5 en out6 en out7 en d le q cl r out15 en output enable switch matrix s d1 q d0 d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 d q clk s d1 q d0 d4 decode d le q cl r out0 en d le out0 b0 q d le q out0 b1 d le q out0 b2 d le q out0 b3 d le out1 b0 q d le q cl r out14 en d le out15 b0 q d le out15 b1 q d le out15 b2 q d q clk s d1 q d0 s d1 q d0 d le out15 b3 q s d1 q d0 out8 en out9 en out10 en out11 en out12 en out13 en out14 en out15 en a3 output addre s s reset (output enable) 01070-011 f i gure 4 . l o gic d i agr a m
ad8114/ad8115 r e v. b | pa ge 8 o f 3 2 absolute maximum ratings table 7. p a r a m e t e r r a t i n g supply voltage 12.0 v internal power dissip a tion 1 ad8114/ad811 5 100-lead plastic lqfp (st) 2.6 w input voltage v s output short-ci rcuit duration observ e pow er derating curves storage temperature range 2 ?65c to +125c 1 specif ication is f o r d e vice in f r ee air ( t a = 25 c) : 100-lead pla s tic lqfp (st): ja = 40c/ w. 2 maximum reflow t e mperatures are to jedec industry standard j-std-020. s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . maximum power dissipation the max i m u m p o w e r t h a t can b e s a fely di ssi p a t e d b y t h e ad8114/ad81 15 is limi t e d b y th e as s o c i a t e d r i s e in j u n c tio n t e m p era t ur e . th e maxim u m s a fe j u n c t i on t e m p era t ur e fo r p l a s ti c e n ca ps ula t ed d e v i c e s i s d e t e rm i n ed b y th e gla s s t r a n si ti o n t e m p era t ur e o f th e plas tic, a p p r o x ima t e l y 125c. t e m p o r a r il y exce e d i n g t h is l i m i t m a y c a us e a sh if t i n p a ramet r ic p e r f o r manc e d u e t o a chan ge i n t h e st r e s s es exer t e d on t h e di e b y t h e p a cka g e . e x ceedin g a j u nc tio n t e m p er a t u r e o f 125c f o r a n ext e n d e d p e r i o d c a n re su lt in de v i c e f a i l u r e. w h ile t h e ad8 114/ad8115 a r e in t e r n al l y sh o r t-cir c ui t prote c te d, th i s m a y n o t be s u ffi c i e n t t o gua r a n t e e th a t th e m a x i m u m j u n c t i o n t e m p er a t ur e (125c) is n o t exceeded u n der a l l c o n d i t i ons . t o en sur e p r op er o p era t i o n, i t i s ne ce s s a r y t o ob s e r ve t h e m a x i m u m p o w e r d e r a t i n g c u r v e s s h ow n i n fi g u r e 5 . t j = 125 c ambient temperature ( c) m a xim u m pow e r d i ssipa tion ( ) 5 4 3 2 1 0 ? 5 0 ? 40 ?30 ? 20 ?10 0 10 20 30 40 50 60 70 80 90 01070-004 f i gure 5. m a xi m u m p o wer d i s s i pat i on v s . t e mpe r atu r e esd caution esd (electrostatic discharge) se nsit ive device . electrostatic charges as hig h as 4000 v readily accumulate on the human bod y and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circ uitry, permanent dama ge may occur on devices subjected to high energy electrostatic di scharge s . ther efore, pro p er esd precautions are rec o m m ended to avoid performan c e degradation or l o ss of functiona l ity.
ad8114/ad8115 r e v. b | pa ge 9 o f 3 2 pin conf iguration and fu nction descriptions 01070-005 nc = no connect r eset ce data out clk data in up date ser /pa r nc nc nc nc nc nc nc nc nc a0 a1 a2 a3 d0 d1 d2 d3 d4 26 a v c c 13/14 27 out13 28 a vee12/13 29 out12 30 a v c c 11/12 31 out11 32 a vee10/11 33 out10 34 a v c c 09/10 35 out09 36 a vee08/09 37 out08 38 a v c c 07/08 39 out07 2 dgnd 3 agnd 4 in08 7 agnd 6 in09 5 agnd 1 dvcc 8 in10 9 agnd 10 in11 12 in12 13 agnd 14 in13 15 agnd 16 in14 17 agnd 18 in15 19 agnd 20 avee 21 avcc 22 avcc15 23 out15 24 avee14/15 25 out14 11 agnd 74 dgnd dvcc 73 agnd 72 in07 69 agnd 70 in06 71 agnd 75 68 in05 67 agnd 66 in04 64 in03 63 agnd 62 in02 61 agnd 60 in01 59 agnd 58 in00 57 agnd 56 avee 55 avcc 54 avcc00 53 out00 52 avee00/01 51 out01 65 agnd 40 a vee06/07 41 out06 42 a v c c 05/06 43 out05 44 a vee04/05 45 out04 46 a v c c 03/04 47 out03 48 a vee02/03 49 out02 50 a v c c 01/02 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pin 1 ad8114/ad8115 top view (not to scale) f i gure 6. pin config ur ation
ad8114/ad8115 rev. b | page 10 of 32 table 8. pin function descriptions pin no. mnemonic pin description 58, 60, 62, 64, 66, 68, 70, 72, 4, 6, 8, 10, 12, 14, 16, 18 inxx analog inputs. xx = channels 00 through 15. 96 data in serial data input, ttl compatible. 97 clk clock, ttl compatible. falling edge triggered. 98 data out serial data out, ttl compatible. 95 update enable (transparent) low. allows serial regi ster to connect directly to switch matrix. data latched when high. 100 reset disable outputs, active low. 99 ce chip enable, enable low. must be low to clock in and latch data. 94 ser /par selects serial data mode, low or parallel data mode, high. must be connected. 53, 51, 49, 47, 45, 43, 41, 39, 37, 35, 33, 31, 29, 27, 25, 23 outyy analog outputs. yy = channels 00 through 15. 3, 5, 7, 9, 11, 13, 15, 17, 19, 57, 59, 61, 63, 65, 67, 69, 71, 73 agnd analog ground for inputs and switch matrix. must be connected. 1, 75 dvcc +5 v for digital circuitry. 2, 74 dgnd ground for digital circuitry. 20, 56 avee ?5 v for inp uts and switch matrix. 21, 55 avcc +5 v for inp uts and switch matrix. 54, 50, 46, 42, 38, 34, 30, 26, 22 avccxx/yy +5 v for output amplifie r that is shared by channels xx and yy. must be connected. 52, 48, 44, 40, 36, 32, 28, 24 aveexx/yy C5 v for output amplifie r that is shared by channels xx and yy. must be connected. 84 a0 parallel data input, ttl compatible (output select lsb). 83 a1 parallel data input, ttl compatible (output select). 82 a2 parallel data input, ttl compatible (output select). 81 a3 parallel data input, ttl compatible (output select msb). 80 d0 parallel data input, ttl compatible (input select lsb) 79 d1 parallel data input, ttl compatible (input select). 78 d2 parallel data input, ttl compatible (input select). 77 d3 parallel data input, ttl compatible (input select msb). 76 d4 parallel data input, tt l compatible (output enable). 85 to 93 nc no connect.
ad8114/ad8115 rev. b | page 11 of 32 typical perf orm ance cha r acte ristics frequency (mhz) 1 0.1 gain ( d b) 1 1 0 100 1000 ?1 0 ?2 ?3 ?4 ?5 ?6 ?7 v o as shown r l = 150 ? gain flatness 2v p-p 200mv p-p ? 0.2 0.2 0.1 0 ? 0.1 ? 0.3 ? 0.4 ? 0.5 fla t n ess ( d b ) ? 0.6 01070-012 f i g u re 7. a d 81 14 f r equenc y r e s p ons e , r l = 150 ? frequency (mhz) gain ( d b) ?7 ?3 1 0 ?1 ?2 ?4 ?5 ?6 ? 0.6 ? 0.2 0.2 0.1 0 ? 0.1 ? 0.3 ? 0.4 ? 0.5 fla tn ess ( d b ) 2 3 0.1 1 1 0 100 1000 0.3 0.4 gain flatness 2v p-p 200mv p-p v o as shown r l = 1k ? 01070-013 f i g u re 8. a d 81 14 f r equenc y r e s p ons e , r l = 1 k? frequency (mhz) gain ( d b) ?3 1 0 ?1 ?2 ?4 ?5 ?6 2 3 0.1 1 1 0 100 1000 4 r l = 1k ? r l = 150 ? v o = 200mv p-p r l as shown c l = 18pf 01070-014 f i g u re 9. a d 81 14 f r equenc y r e s p ons e v s . l oad impedan ce frequency (mhz) 2 0.1 gain ( d b) 1 1 0 100 1000 0 1 ?1 ?2 ?3 ?4 ?5 ?6 ?8 ?7 v o as shown r l = 150 ? gain flatness 200mv p-p 2v p-p 2v p-p 200mv p-p 0 0.5 0.4 0.3 0.2 0.1 ?0.1 ?0.2 ?0.3 ?0.4 fla t n ess ( d b ) ?0.5 01070-015 f i gur e 1 0 . ad81 15 f r e q ue nc y re sp onse , r l = 150 ? frequency (mhz) 3 0.1 gain ( d b) 1 1 0 100 1000 1 2 0 ?1 ?2 ?3 ?4 ?5 ?7 ?6 v o as shown r l = 1k ? gain flatness 200mv p-p 2v p-p 2v p-p 200mv p-p 0 0.5 0.4 0.3 0.2 0.1 ?0.1 ?0.2 ?0.3 ?0.4 fla tn ess ( d b ) ?0.5 01070-016 f i gur e 1 1 . ad81 15 f r e q ue nc y re sp onse , r l = 1 k? frequency (mhz) gain ( d b) ?4 4 2 0 ?2 ?6 ?8 ?1 0 6 8 0.1 1 1 0 100 1000 10 r l = 1k ? r l = 150 ? v o = 200mv p-p r l as shown c l = 18pf 01070-017 f i gur e 1 2 . ad81 15 f r e q ue nc y re sp onse vs . l o a d im p e da nc e
ad8114/ad8115 rev. b | page 12 of 32 frequency (mhz) cros s t alk (db) ?70 ?50 ?60 ?80 ?90 ? 100 0.1 1 1 0 100 1000 all hostile 0 ?40 ?30 ?20 ?10 adjacent r l = 1k ? r t = 37.5 ? 01070-018 f i gur e 1 3 . ad81 14 cr o ssta l k vs . f r e q ue nc y fundamental frequency (mhz) distortion (dbc) ?50 ?30 ?60 ?80 ? 100 11 0 2nd harmonic 0 50 3rd harmonic ?20 ?40 ?70 ?90 ?10 v o = 2v p-p r l = 150 ? 01070-019 f i gur e 1 4 . ad81 14 di st or tio n vs . f r e q ue nc y 0 5 10 15 20 25 30 35 40 45 5ns/div 0.1%/d iv 01070-020 v o = 2v step r l = 150 ? f i gur e 1 5 . ad81 14 se ttl ing ti me frequency (mhz) cros s t alk (db) ?70 ?50 ?60 ?80 ?90 ? 100 0.1 1 1 0 100 1000 all hostile 0 ?40 ?30 ?20 ?10 adjacent r l = 1k ? r t = 37.5 ? 01070-021 f i gur e 1 6 . ad81 15 cr o ssta l k vs . f r e q ue nc y fundamental frequency (mhz) dis t ortion (dbc) ?5 0 ?3 0 ?6 0 ?8 0 ?100 11 0 2nd harmonic 0 50 3rd harmonic ?2 0 ?4 0 ?7 0 ?9 0 ?1 0 v o = 2v p-p r l = 150 ? 01070-022 f i gur e 1 7 . ad81 15 di st or tio n vs . f r e q ue nc y 5ns/div 0 5 10 15 20 25 30 35 40 45 0.1%/d iv 01070-023 v o = 2v step r l = 150 ? f i gur e 1 8 . ad81 15 se ttl ing ti me
ad8114/ad8115 rev. b | page 13 of 32 frequency (mhz) inp u t imp e dance ( ? ) 100k 1m 10k 1k 100 10 500 0.1 1 100 01070-024 f i gur e 1 9 . ad81 14 input impedan c e vs . f r equenc y frequency (mhz) 1 0.1 outp ut imp e dance ( ? ) 1 1 0 100 1000 0.1 10 100 1000 01070-025 f i gur e 2 0 . ad81 14 output im p e da nc e , ena b le d vs . f r e q ue nc y frequency (mhz) 0.1 outp ut imp e dance ( ? ) 1 1 0 100 1000 10 100 1m 1k 10k 100k 01070-026 f i gur e 2 1 . ad81 14 output im p e da nc e , di sa bl e d vs . f r e q ue nc y frequency (mhz) 0.1 inp u t imp e dance ( ? ) 1 1 0 100 500 100 1k 10k 100k 1m 01070-027 f i gur e 2 2 . ad81 15 input impedan c e vs . f r equenc y frequency (mhz) 0.1 outp ut imp e dance ( ? ) 1 1 0 100 1000 10 100 1000 1 0.1 01070-028 f i gur e 2 3 . ad81 15 output im p e da nc e , ena b le d vs . f r e q ue nc y frequency (mhz) 0.1 outp ut imp e dance ( ? ) 1 1 0 100 1000 10 100 1k 10k 100k 1m 01070-029 f i gur e 2 4 . ad81 15 output im p e da nc e , di sa bl e d vs . f r e q ue nc y
ad8114/ad8115 rev. b | page 14 of 32 frequency (mhz) off is olation (db) ?110 ?9 0 ?100 ?120 ?130 ?140 0.1 1 1 0 ?8 0 100 500 ?7 0 ?6 0 ?5 0 ?4 0 01070-030 f i gur e 2 5 . ad81 14 o ff iso l a t i o n, input - output frequency (mhz) p s rr (db) ? 100 0.03 10 0.1 1 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?psrr +psrr 01070-031 f i gur e 2 6 . ad81 14 p s rr vs . f r e q ue nc y frequency (hz) 170 10 10 100 volta ge n o ise ( n v/ hz) 30 1k 10k 100k 1m 10m 16nv/ hz 50 70 90 110 130 150 01070-032 f i gur e 2 7 . ad81 14 v o l t a g e no i s e vs . f r e q ue nc y frequency (mhz) off is olation (db) ?110 ?9 0 ?100 ?120 ?130 ?140 0.1 1 1 0 ?8 0 100 500 ?7 0 ?6 0 ?5 0 ?4 0 01070-033 f i gur e 2 8 . ad81 15 o ff iso l a t i o n, input - output frequency (mhz) p s rr (db) ? 100 0.03 10 0.1 1 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ? psrr +psrr 01070-034 f i gur e 2 9 . ad81 15 p s rr vs . f r e q ue nc y frequency (hz) 170 10 10 100 volta ge n o ise ( n v/ hz) 30 1k 10k 100k 1m 10m 50 70 90 110 130 150 01070-035 18nv/ hz f i gur e 3 0 . ad81 15 v o l t a g e no i s e vs . f r e q ue nc y
ad8114/ad8115 rev. b | page 15 of 32 01070-036 0.10v 0.05v 0v ? 0.05v ? 0.10v ? 0.15v 0.15v v o = 200mv step r l = 150 ? 50mv 25ns f i gur e 3 1 . ad81 14 p u l s e re sp onse , sma l l si gnal 01070-037 1.0v 0.5v 0v ? 0.5v ? 1.0v ? 1.5v 1.5v v o = 2v step r l = 150 ? 500mv 25ns f i gur e 3 2 . ad81 14 p u l s e re sp onse , la r g e si gna l 01070-038 0v +5v ?1v ?0v +1v input 1 at +1v input 0 at ?1v v out update 10ns f i gur e 3 3 . ad81 14 s w i t c h i n g t i m e 01070-039 0.10v 0.05v 0v ? 0.05v ? 0.10v ? 0.15v 0.15v v o = 200mv step r l = 150 ? 50mv 25ns f i gur e 3 4 . ad81 15 p u l s e re sp onse , sma l l si gnal 01070-040 1.0v 0.5v 0v ? 0.5v ? 1.0v ? 1.5v 1.5v v o = 200mv step r l = 150 ? 500mv 20ns f i gur e 3 5 . ad81 15 p u l s e re sp onse , la r g e si gna l 01070-041 0v +5v ?2v ?0v +2v input 1 at +1v input 0 at ?1v v out update 10ns f i gur e 3 6 . ad81 15 s w i t c h i n g t i m e
ad8114/ad8115 rev. b | page 16 of 32 01070-042 0v 0.05v 0v ? 0.05v 5v update 50ns f i g u re 37. a d 8 1 1 4 switch ing t r ans i e n t (glit ch) offset voltage (mv) 0 ?1 2 ?10 fre q ue ncy 20 40 60 80 100 120 140 160 180 200 220 240 260 ?8 ?6 ?4 ?2 0 2 4 6 8 10 01070-043 f i gur e 3 8 . ad81 14 o ffse t v o l t a g e di st r i butio n offset voltage drift ( v/ c) 0 ?20 fre q ue ncy 4 8 12 16 20 24 28 32 36 40 44 ? 1 6 ? 12 ? 8 ?4 0 4 8 1 2 1 6 2 0 01070-044 f i g u re 39. a d 8 1 1 4 o f f s et v o lt ag e d r if t d i s t ribut i on (? 40 c to +8 5c ) 01070-045 0v 0.05v 0v ? 0.05v 5v update 50ns f i g u re 40. a d 8 1 1 5 switch ing t r ans i e n t (glit ch) offset voltage (mv) 0 ?14 ?10 ?12 fre q ue ncy 20 40 60 80 100 120 140 160 180 200 220 240 ?8 ?6 ? 4 ?2 0 2 4 10 12 14 16 6 8 18 01070-046 f i gur e 4 1 . ad81 15 o ffse t v o l t a g e di st r i butio n offset voltage drift ( v/ c) 0 fre q ue ncy 4 8 12 16 20 24 28 32 36 40 44 ?12 ? 8 ? 4 0 4 8 12 16 20 01070-047 f i g u re 42. a d 8 1 1 5 o f f s et v o lt ag e d r if t d i s t ribut i on (? 40 c to +8 5c )
ad8114/ad8115 rev. b | page 17 of 32 i/o sche matics esd esd input v cc avee 01070-006 f i g u re 43. a n a l og i n put esd esd output v cc avee 01070-007 f i g u re 44. a n a l og o u t p ut esd esd v cc reset 20k ? dgnd 01070-008 f i gure 4 5 . reset inp u t esd esd input v cc dgnd 01070-009 f i gure 4 6 . l o gi c inp u t esd esd output v cc dgnd 2k ? 01070-010 f i gure 4 7 . l o gi c o u tput
ad8114/ad8115 rev. b | page 18 of 32 theory of operation the ad8114 (g = 1) and ad8115 (g = 2) are crosspoint arrays with 16 outputs, each of which can be connected to any one of 16 inputs. organized by output row, 16 switchable transconductance stages are connected to each output buffer in the form of a 16-to-1 multiplexer. each of the 16 rows of transconductance stages are wired in parallel to the 16 input pins, for a total array of 256 transconductance stages. decoding logic for each output selects one (or none) of the transconductance stages to drive the output stage. the transconductance stages are npn-input differential pairs, sourcing current into the folded cascode output stage. the compensation network and emitter follower output buffer are in the output stage. voltage feedback sets the gain, with the ad8114 configured as a unity gain follower, and the ad8115 configured as a gain-of-2 amplifier with a feedback network. this architecture provides drive for a reverse-terminated video load (150 ?), with low differential gain and phase error for relatively low power consumption. power consumption is further reduced by disabling outputs and transconductance stages that are not in use. the user will notice a small increase in input bias current as each transconductance stage is enabled. features of the ad8114 and ad8115 simplify the construction of larger switch matrices. the unused outputs of both devices can be disabled to a high impedance state, allowing the outputs of multiple ics to be bused together. in the case of the ad8115, a feedback isolation scheme is used so that the impedance of the gain-of-2 feedback network does not load the output. because no additional input buffering is necessary, high input resistance and low input capacitance are easily achieved without additional signal degradation. to control enable glitches, it is recommended that the disabled output voltage be maintained within its normal enabled voltage range (3.3 v). if necessary, the disabled output can be kept from drifting out of range by applying an output load resistor to ground. a flexible ttl-compatible logic interface simplifies the programming of the matrix. both parallel and serial loading into a first rank of latches programs each output. a global latch simultaneously updates all outputs. a power-on reset pin is available to avoid bus conflicts by disabling all outputs. applications the ad8114/ad8115 have two options for changing the programming of the crosspoint matrix. in the first option a serial word of 80 bits can be provided that will update the entire matrix each time. the second option allows for changing a single outputs programming via a parallel interface. the serial option requires fewer signals, but more time (clock cycles) for changing the programming, while the parallel programming technique requires more signals, but can change a single output at a time and requires fewer clock cycles to complete programming. serial programming the serial programming mode uses the device pins ce , clk, data in, update , and ser /par. the first step is to assert a low on ser /par to enable the serial programming mode. ce for the chip must be low to allow data to be clocked into the device. the ce signal can be used to address an individual device when devices are connected in parallel. the update signal should be high during the time that data is shifted into the devices serial port. although the data will still shift in when update is low, the transparent, asynchronous latches will allow the shifting data to reach the matrix. this will cause the matrix to try to update to every intermediate state as defined by the shifting data. the data at data in is clocked in at every down edge of clk. a total of 80 bits must be shifted in to complete the programming. for each of the 16 outputs, there are four bits (d0 to d3) that determine the source of its input followed by one bit (d4) that determines the enabled state of the output. if d4 is low (output disabled), the four associated bits (d0 to d3) do not matter because no input will be switched to that output. the most significant output address data is shifted in first, and then following in sequence until the least significant output address data is shifted in. at this point update can be taken low, which will cause the programming of the device according to the data that was just shifted in. the update registers are asynchronous, and when update is low (and ce is low), they are transparent.
ad8114/ad8115 rev. b | page 19 of 32 if more than one ad8114/ad8115 device is to be serially programmed in a system, the data out signal from one device can be connected to the data in of the next device to form a serial chain. all of the clk, ce , update , and ser /par pins should be connected in parallel and operated as described above. the serial data is input to the data in pin of the first device of the chain, and it will ripple on through to the last. therefore, the data for the last device in the chain should come at the beginning of the programming sequence. the length of the programming sequence (80 bits) will be multiplied by the number of devices in the chain. parallel programming while using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. in fact, parallel programming allows the modification of a single output at a time. since this takes only one clk/ update cycle, significant time savings can be realized by using parallel programming. one important consideration in using parallel programming is that the reset signal does not reset all registers in the ad8114/ad8115. when taken low, the reset signal will only set each output to the disabled state. this is helpful during power-up to ensure that two parallel outputs will not be active at the same time. after initial power-up, the internal registers in the device will generally have random data, even though the reset signal was asserted. if parallel programming is used to program one output, then that output will be properly programmed, but the rest of the device will have a random program state depending on the internal register content at power-up. therefore, when using parallel programming, it is essential that all outputs be programmed to a desired state after power-up. this will ensure that the programming matrix is always in a known state. from then on, parallel programming can be used to modify a single output or more at a time. in similar fashion, if both ce and update are taken low after initial power-up, the random power-up data in the shift register will be programmed into the matrix. therefore, to prevent the crosspoint from being programmed into an unknown state, do not apply low logic levels to both ce and update after power is initially applied. programming the full shift register one time to a desired state by either serial or parallel programming after initial power-up will eliminate the possibility of programming the matrix to an unknown state. to change an outputs programming via parallel programming, ser /par and update should be taken high and ce should be taken low. the clk signal should be in the high state. the 4-bit address of the output to be programmed should be put on a0 to a3. the first four data bits (d0 to d3) should contain the information that identifies the input that gets programmed to the output that is addressed. the fourth data bit (d4) will determine the enabled state of the output. if d4 is low (output disabled), then the data on d0 to d3 does not matter. after the desired address and data signals have been established, they can be latched into the shift register by a high to low transition of the clk signal. the matrix will not be programmed, however, until the update signal is taken low. it is thus possible to latch in new data for several or all of the outputs first via successive negative transitions of clk while update is held high, and then have all the new data take effect when update goes low. this technique should be used when programming the device for the first time after power-up when using parallel programming. power-on reset when powering up the ad8114/ad8115, it is usually desirable to have the outputs come up in the disabled state. when taken low, the reset pin will cause all outputs to be in the disabled state. however, the reset signal does not reset all registers in the ad8114/ad8115. this is important when operating in the parallel programming mode. please refer to that section for information about programming internal registers after power- up. serial programming will program the entire matrix each time, so no special considerations apply. since the data in the shift register is random after power-up, it should not be used to program the matrix, or the matrix can enter unknown states. to prevent this, do not apply logic low signals to both ce and update initially after power-up. the shift register should first be loaded with the desired data, and then update can be taken low to program the device. the reset pin has a 20 k? pull-up resistor to dvdd that can be used to create a simple power-up reset circuit. a capacitor from reset to ground will hold reset low for some time while the rest of the device stabilizes. the low condition will cause all the outputs to be disabled. the capacitor will then charge through the pull-up resistor to the high state, thus allowing full programming capability of the device. gain selection the 16 16 crosspoints come in two versions, depending on the gain of the analog circuit paths that is desired. the ad8114 device is unity gain and can be used for analog logic switching and other applications where unity gain is desired. the ad8114 can also be used for the input and interior sections of larger crosspoint arrays where termination of output signals is not usually used. the ad8114 outputs have very high impedance when their outputs are disabled. the ad8115 can be used for devices that will be used to drive a terminated cable with its outputs. this device has a built-in gain
ad8114/ad8115 rev. b | page 20 of 32 o f 2 t h a t e l imina t es t h e n e e d fo r a ga in-o f-2 b u f f er t o dr i v e a vid e o li n e . i t s h i g h o u t p u t dis a b l e d i m p e dan c e mini mi zes sig n a l d e grad a t i o n wh en pa ralle l in g ad di ti o n al o u t p u t s. creating l a rger crosspoint ar rays the ad8114 /ad8115 a r e hig h den s i t y b u ildin g b l o c ks f o r cr ea tin g cr os sp o i n t a r ra ys o f dim e n s io n s la rg er tha n 16 16. v a r i ou s f e a t u r e s , su ch a s output d i s a bl e, c h ip e n abl e , a n d g a i n - of - 1 an d g a i n - o f - 2 opt i ons , are u s e f u l f o r cre a t i ng l a r g e r ar r a y s . w h en r e quir e d fo r c u st o m izin g a cr ossp o i n t a r ra y siz e , t h e y c a n be us e d wi t h t h e ad8108 and ad8109, a p a ir o f (uni ty ga in and ga in-o f-2) 8 8 video cr os s p o i n t s w i t c h es, o r wi th t h e ad811 0 a nd ad8111, a p a ir o f (uni ty ga in and ga in-o f-2) 16 8 video c r o ssp oin t s w i t c h e s . the f i rs t co n s i d era t io n in co ns t r uc t i n g a la rg er cr os s p o i n t is t o deter m i n e t h e mini m u m n u mb er o f de vice s r e q u ir e d . t h e 16 16 a r c h i t ec t u r e o f th e ad8114/ad8115 co n t a i n s 256 p o in ts, which is a fac t or o f 64 g r ea t e r tha n a 4 1 cr os s p o i n t (o r m u l t i p lexer ) . t h e p c b o a r d a r e a , p o wer co n s u m p t ion, an d desig n ef fo r t s a vin g s a r e r e adily a p p a r e n t w h e n co m p a r e d t o us i n g th ese s m all e r d evi ce s . f o r a n o n b lo ck i n g cr ossp o i n t , t h e n u m b er o f p o in ts r e q u ir e d is t h e p r o d uc t o f t h e n u m b er o f in p u ts m u l t i p lie d b y t h e n u m b er of output s . n o nbl o ck i n g re q u i r e s t h a t t h e pro g r a m m i ng of a g i ve n i n put to one or more output s d o e s not re s t r i c t t h e a v a i lab i li ty o f tha t in p u t t o b e a s o ur ce f o r a n y o t h e r o u t p u t s. s o me no nbl o ck i n g c r o ssp oi n t a r ch ite c tu re s w i l l re qu i r e more t h a n t h is mini m u m as calc u l a t e d ab o v e . als o , t h er e a r e b l o c king a r c h i t ec t u r e s tha t ca n be co n s tr uct e d w i th f e w e r d evi ce s th a n th i s m i n i m u m . t h ese s y s t em s ha v e co nn ect i vi t y a v a i l a b l e o n a s t a t is t i ca l basis t h a t is det e r m in e d w h e n desig n in g t h e o v eral l sys t em. the basic con c ep t in co n s tr uc tin g la rg er cr os s p o i n t a r ra ys is t o co n n ec t in p u t s in pa ralle l in a h o ri z o n t al di r e ctio n a n d t o w i r e - o r t h e o u t p u t s t o g e t h er i n t h e v e r t ical dir e c t ion. th e me a n i n g o f h o r i zon t a l and ver t ica l ca n b e st b e u n dersto o d b y lo ok in g a t a dia g ra m. f i gu r e 48 il l u s t ra t e s this co ncep t f o r a 32 32 cr os s p o i n t a r ra y tha t us es f o ur ad8114s o r ad8115s. ad8114 or ad8115 ad8114 or ad8115 ad8114 or ad8115 ad8114 or ad8115 16 16 16 16 r term in 00?15 16 16 r term in 16?31 16 16 16 16 01070-048 f i gur e 4 8 . 32 32 cr o ssp oi nt a r r a y u s i n g ad81 14 o r f o ur ad811 5 s the in p u ts a r e e a c h uniq ue l y assig n e d t o each o f th e 32 in p u ts of t h e t w o d e v i c e s an d te r m i n a t e d a ppropr i ately . t h e output s are w i re d - o r e d to ge t h e r i n p a i r s . t h e output f r om on ly one of a w i r e -or e d p a ir sh o u l d b e enab le d a t an y g i ve n t i m e . t h e de v i c e pro g r a m m i n g s o f t w a re m u st b e prop e r l y w r i tte n to c a u s e th i s t o h a p p e n .
ad8114/ad8115 rev. b | page 21 of 32 16 r term in 00?15 8 8 in 16?31 in 32?47 in 48?63 in 64?79 in 80?95 in 96? 111 in 112?127 8 8 8 8 rank 2 32:16 nonblocking (32:32 blocking) rank 1 (8 ad8114) 128:32 16 r term 8 8 16 r term 8 8 16 r term 8 8 16 r term 8 8 16 r term 8 8 16 r term 8 8 16 r term 8 8 ad8115 8 1k ? 8 1k ? 8 1k ? 8 1k ? ad8115 out 00e 1 5 nonblocking additional 16 outputs (subject to blocking) ad8114 ad8114 ad8114 ad8114 ad8114 ad8114 ad8114 ad8114 01070-049 f i gur e 4 9 . nonblo ck i n g 12 8 16 a r r a y (1 28 32 bl oc k i ng) u s in g ad di t i o n a l cr o ssp o i n t de v i ces in t h e desig n can lo w e r t h e n u mb e r of output s t h at m u st b e w i re - o r e d to ge t h e r . f i g u re 4 9 s h o w s a b l o c k dia g ra m o f a sys t em usin g eig h t ad8114s an d tw o ad8115s to cr ea t e a n o n b l o c k ing, ga in-o f-2, 128 16 c r o ssp oin t t h a t re st r i c t s t h e wire -or ing a t t h e ou t p ut to on ly fo u r o u t p u t s. a d d i t i on a l ly , b y u s i n g t h e l o we r e i g h t output s f r om e a ch of t h e tw o r a n k 2 ad8115s, a b l o c k i ng 128 32 cr os s p o i n t a r ra y ca n be r e aliz ed . th er e a r e , h o w e v e r , so m e d r a w ba cks t o th i s t e chni q u e . the o f fs et v o l t a g es o f t h e v a r i o u s cas c ade d de v i ces wi l l acc u m u la te, a nd t h e b a ndw id t h li mi t a t i o n s o f t h e d e vices wil l com p o u nd . i n addi tio n , t h e extra de vices wil l co n s u m e m o r e c u r r en t and t a k e u p m o re b o a r d sp ac e. on ce a g a i n, t h e o v era l l sy st em d e sig n sp e c if ica t i o n s wi l l det e r m ine h o w t o m a ke th e v a ri o u s tra d eo f f s. multichannel video the exce l l en t video s p ecif ica t ion s o f th e ad81 14/ad8115 ma k e th em id eal ca n d i d a t e s f o r cr ea tin g co m p os i t e v i d e o cr os s p o i n t swi t ch es. th e s e ca n b e made q u i t e den s e b y t aki n g ad van t a g e o f th e ad8114 /ad8115 s hig h le v e l o f in t e g r a t io n an d t h e fac t t h a t co m p osi t e v i de o r e q u ir es o n l y o n e cr os s p oin t cha nne l p e r sys t em vide o cha nne l . th er e a r e, h o we v e r , o t h e r vide o fo r m a t s tha t c a n be r o u t ed wi t h t h e ad8114/ad8115 req u ir in g m o r e t h an one c r o ssp oin t chan nel p e r v i de o chan nel. s o m e sys t em s u s e twis t e d-p a ir wir i n g t o ca r r y vide o sig n als. th e s e sys t e m s u t ilize dif f er en tia l sig n als a nd can lo w e r cos t s b e c a us e t h e y us e lo w e r co st cables, co nn e c to rs a nd ter m ina t ion m e tho d s. they als o ha v e t h e a b ili t y t o lo w e r cr os s t al k and r e je c t co m m o n -m o d e s i gn al s , wh i c h ca n be i m po r t a n t f o r eq ui p m en t t h a t o p era t es in n o isy en v i r o nmen ts o r w h er e c o mm on- m o d e v o l t a g es a r e p r es en t b e tw e e n t r a n smi t t i n g an d r e cei v in g eq ui p m en t . i n s u ch sys t em s , t h e vide o sig n als a r e dif f er en t i al; t h er e is a p o s i t i ve and ne g a t i ve ( o r i n ve r t e d ) ve rs i o n of t h e s i g n a l s . t h e s e c o m p l e me n t ar y s i g n a l s are t r ans m i tte d on to e a ch of t h e t w o w i re s of t h e t w i s te d p a i r , y i el d i ng a f i r s t - ord e r z e ro c o m m on - m o de v o l t a g e . a t t h e r e cei v e e n d , t h e sig n als a r e dif f er en t i al l y r e cei v e d and con v er te d b a ck in to a sin g le- e n d e d sig n a l . w h en s w i t ching t h e s e dif f er en t i al sig n als, tw o cha nne ls a r e r e q u i r ed in t h e s w i t c h in g e l em en t t o h a n d le t h e t w o di f f e r e n ti al
ad8114/ad8115 rev. b | page 22 of 32 signals that make up the video channel. thus, one differential video channel is assigned to a pair of crosspoint channels, both input and output. for a single ad8114/ad8115, eight differential video channels can be assigned to the 16 inputs and 16 outputs. this will effectively form an 8 8 differential crosspoint switch. programming such a device will require that inputs and outputs be programmed in pairs. this information can be deduced by inspection of the programming format of the ad8114/ad8115 and the requirements of the system. there are other analog video formats requiring more than one analog circuit per video channel. one 2-circuit format that is commonly being used in systems such as satellite tv, digital cable boxes, and higher quality vcrs is called s-video or y/c video. this format carries the brightness (luminance or y) portion of the video signal on one channel and the color (chrominance, chroma, or c) on a second channel. since s-video also uses two separate circuits for one video channel, creating a crosspoint system requires assigning one video channel to two crosspoint channels, as in the case of a differential video system. aside from the nature of the video format, other aspects of these two systems will be the same. there are yet other video formats using three channels to carry the video information. video cameras produce rgb (red, green, blue) directly from the image sensors. rgb is also the usual format used by computers internally for graphics. rgb can be converted to y, r-y, b-y format, sometimes called yuv format. these 3-circuit video standards are referred to as component analog video. the component video standards require three crosspoint channels per video channel to handle the switching function. in a fashion similar to the 2-circuit video formats, the inputs and outputs are assigned in groups of three, and the appropriate logic programming is performed to route the video signals. crosstalk many systems, such as broadcast video, that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the others in the system. crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. when there are many signals in close proximity in a system, as will undoubtedly be the case in a system that uses the ad8114/ad8115, the crosstalk issues can be quite complex. a good understanding of the nature of crosstalk and some definition of terms is required to specify a system that uses one or more ad8114/ad8115s. types of crosstalk crosstalk can be propagated by means of any of three methods. these fall into the categories of electric field, magnetic field, and sharing of common impedances. this section will explain these effects. every conductor can be both a radiator of electric fields and a receiver of electric fields. the electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance (e.g., free space) and couples with the receiver and induces a voltage. this voltage is an unwanted crosstalk signal in any channel that receives it. currents flowing in conductors create magnetic fields that circulate around the currents. these magnetic fields will then generate voltages in any other conductors whose paths they link. the undesired induced voltages in these other channels are crosstalk signals. the channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. the power supplies, grounds, and other signal return paths of a multichannel system are generally shared by the various channels. when a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance. all these sources of crosstalk are vector quantities, so the magnitudes cannot simply be added together to obtain the total crosstalk. in fact, there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk. areas of crosstalk for a practical ad8114/ad8115 circuit, it is required that it be mounted to some sort of circuit board to connect it to power supplies and measurement equipment. great care has been taken to create a characterization board (also available as an evaluation board) that adds minimum crosstalk to the intrinsic device. this, however, raises the issue that a systems crosstalk is a combination of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted. it is important to try to separate these two areas of crosstalk when attempting to minimize its effect. in addition, crosstalk can occur among the inputs to a crosspoint and among the output. it can also occur from input to output. techniques will be discussed for diagnosing which part of a system is contributing to crosstalk.
ad8114/ad8115 rev. b | page 23 of 32 meas uring c r os s t alk cr osst a l k is m e asur e d b y a p ply i n g a sig n a l t o on e o r m o r e c h a n n e ls a n d m e a s uri n g t h e r e la ti v e str e n g th o f th a t si gnal o n a desir e d s e le c t e d cha nne l . th e me as ur emen t is u s ual l y exp r es s e d as db do wn f r o m t h e ma g n i t u d e o f th e t e s t sig n al . th e cr os s t al k is exp r es s e d b y () () ( ) s atest s asel xt 10 log 20 = w h er e s = j is t h e l a place t r a n s f o r m va r i a b le , as e l (s) is t h e a m p l i t ude o f the cr os s t al k-in d u ced sig n al in t h e s e lec t ed cha nnel, and at e s t ( s ) is t h e am pli t u d e o f t h e t e s t sig n al . i t can b e s e e n t h a t c r o sst a l k i s a f u nc t i o n of f r e q u e nc y , b u t no t a f u nc t i o n of t h e m a g n itu d e of t h e te st s i g n a l ( t o f i r s t ord e r ) . i n a d d i t i on , t h e cr osst a l k sig n a l w i l l ha ve a phas e r e la t i ve t o t h e t e st sig n a l ass o c i a t e d w i t h i t . a netw o r k a n alyzer is m o st co mm onl y us ed to m e as ur e c r o sst a l k o v e r a f r e q u e nc y r a nge of in te re st . i t c a n p r o v ide b o t h ma g n i t u d e and phas e info r m a t i o n a b ou t t h e cro sst a l k sig n a l . a s a cr os sp o i n t sys t em o r de vi c e g r o w s la rg er , t h e n u m b er o f t h e o r e t i ca l cr o s st a l k com b in a t i o n s a nd p e r m u t a t io n s ca n b e c o me e x t r e m ely l a rge. f o r e x am pl e, i n t h e c a s e of t h e 1 6 1 6 ma tr ix o f the ad8114/ad8115, w e can exa m ine the n u m b er o f c r o sst a l k te r m s t h a t c a n b e c o ns i d e r e d for a s i ng l e ch an nel, s a y in00 in p u t. in0 0 is p r og ra mm ed t o co nn ec t t o o n e o f t h e ad8114/ad81 15 o u t p u t s w h ere the m e as ur emen t can be made . f i rs t, we can me as ur e t h e cr os stal k t e r m s as s o c i a t e d wi t h dr i v in g a t e st sig n al in t o eac h of th e o t h e r 15 in p u ts on e a t a tim e w h ile a p p l yin g n o sig n al to in00. w e can th en m e as ur e t h e cr osst a l k t e r m s ass o c i a t e d w i t h dr i v in g a p a ra l l el t e st sig n a l i n to al l 15 o t h e r in p u ts tak e n tw o a t a tim e in al l p o s s i b le co m b ina t io n s , t h e n t h r e e a t a t i m e , et c., u n t i l t h er e is o n l y on e wa y t o dr i v e a tes t sig n al in t o al l 15 o t h e r in p u ts in p a ral l e l . e a ch o f t h e s e c a s e s is leg i t i ma t e ly dif f er en t f r o m t h e ot hers a nd mig h t y i eld a u n iq ue v a l u e d e p e nding o n t h e res o l u t i o n o f t h e m e as ur e m en t sys t em, b u t i t is ha r d l y p r ac t i cal t o m e as ur e al l th e s e t e rm s a n d th en t o s p eci f y th em . i n ad di ti o n , th i s d e scri be s t h e c r o sst a l k m a t r ix for j u st one in pu t chan nel. a s i mi l a r c r o sst a l k m a t r i x c a n b e prop o s e d f o r e v e r y ot he r i n put . in add i t i on, if t h e p o ssi b le com b i n a t io n s and p e r m u t a t io n s fo r co nn e c t i n g in pu ts t o t h e o t h e r (n o t us e d fo r me as ur emen t) o u t p uts a r e t a k e n i n t o co n s idera t io n, t h e n u m b e r s ra t h er qu i c k l y g r o w to a s t r onom i c a l pr op or t i ons . i f a l a r g e r c r o ssp oi n t a r ra y o f m u l t i p le ad8114/ad8 115s is co n s tr uc t e d , t h e n u m b ers g r o w l a rge r st i l l. o b v i ou sly , s o me sub s e t of a l l t h e s e c a s e s m u st b e s e l e c t e d to b e us e d as a gui d e fo r a p r ac t i ca l m e a s ur e o f cr osst a l k. o n e c o mmon me t h o d is to me asu r e a l l ho st i l e c r o sst a l k. thi s te r m m e an s t h a t t h e cr osst a l k t o t h e s e le c t e d cha n nel is m e a s ur e d w h i l e al l ot her sys t em cha n ne ls a r e dr i v en in p a ral l e l . i n g e neral, t h is w i l l y i e l d t h e w o rst cr osst a l k n u m b er , b u t t h is is n o t a l w a y s t h e cas e d u e t o t h e v e c t o r na t u r e o f t h e cr os s t al k sig n al . oth e r use f ul cr os s t alk m e as ur em en t s a r e t h ose cr ea t e d b y o n e n e a r est neig h b or o r b y t h e tw o n e a r est neig h b ors o n ei t h er side. th e s e cr os s t al k m e as ur e m en ts wi l l g e n e ral l y b e hig h er t h an th ose o f m o r e di s t a n t c h a n n e ls, so th ey ca n se r v e a s a w o r s t- ca s e m e a s ur e fo r a n y o t h e r 1-chan n e l o r 2-cha nnel c r osst a l k me a s u r e m e n t s . inp u t and o u t p ut c r os s t alk the f l exi b le p r og ra mmin g ca p a b i li ty o f t h e ad8114/ad8115 ca n be us e d t o dia g n o s e w h et h e r cr os s t al k is o c c u r r i n g m o r e on t h e in p u t si de or t h e o u t p ut side . s o m e exa m pl es a r e i l l u s t ra t i ve . a g i v e n in p u t cha nne l (in07 in t h e mid d le fo r t h is exa m ple) ca n be p r og ra mm e d t o dr i v e o u t07 (als o in t h e middle). th e in p u t t o in07 is j u s t t e r m ina t e d t o g r o u n d ( v ia 50 ? o r 75 ?) a nd n o sig n a l is a p plie d . a l l th e o t h e r i n p u t s a r e d r i v e n i n pa r a ll e l w i th th e s a m e t e s t sig n a l (p rac t ica l ly t h a t is p r o v id e d b y a dist r i b u t i o n a m pl if ier), wi t h a l l ot her o u t p uts excep t ou t07 dis a b l e d . since g r o u nde d in07 is p r og ra mm e d t o dr i v e o u t07, n o sig n al sh o u ld be p r es en t. an y sig n al tha t is p r es en t can be a t tr i b u t ed t o t h e o t h e r 15 h o s t ile in pu t sig n als b e ca us e n o o t h e r o u t p u t s a r e dr i v en. (t h e y a r e all d i s a b l ed . ) t h us, thi s m e th od m e asur e s th e all- ho st i l e in pu t c o n t r i b u t i on to c r o sst a l k i n to i n 0 7 . o f c o u r s e , t h e m e t h o d ca n b e us e d fo r o t h e r i n p u t chan n e ls and com b ina t ions o f h o s t ile in p u t s . f o r o u t p u t cr os s t alk m e as ur em en t , a si n g le in p u t c h a n n e l i s dr i v en (i n00, fo r ex a m ple) a nd a l l o u t p uts o t h e r t h a n a g i ve n o u t p u t (in 07 in th e m i ddl e ) a r e p r ogra m m ed t o co n n ect t o in00. o u t07 is p r og ra mm ed to co nn ec t t o in15 (fa r a w a y f r o m in00), whic h is t e r m ina t e d t o g r o u nd . th us o u t07 s h o u l d n o t ha v e a sig n al p r es e n t sin c e i t is li s t enin g t o a q u ie t in p u t. an y sig n al meas ur ed a t t h e o u t07 ca n be a t tr ib u t e d t o t h e ou t p u t cr os st al k o f t h e o t h e r 16 h o s t i l e o u t p u t s. a g a i n, t h is m e t h o d ca n b e m o dif i e d to m e asur e o t her cha nnels an d o t h e r cr ossp o i n t ma t r ix co m b in a t io n s .
ad8114/ad8115 rev. b | page 24 of 32 effect of i m p e da nc es on c r o s s t alk the i n p u t si de c r o sst a l k can b e i n f l uen c e d b y t h e o u t p ut im p e dan c e o f t h e s o ur ces t h a t dr i v e t h e in pu ts . the lo w e r t h e im p e dan c e o f t h e dr i v e s o ur c e , t h e lo w e r t h e ma g n i t u d e o f t h e c r o sst a l k. t h e d o minan t c r o sst a l k me c h anis m on t h e i n p u t s i de i s c a p a c i t i ve c o upl i ng . t h e h i g h i m p e d a nc e i n put s d o not h a v e sig n if ican t c u r r en t f l o w t o cr e a te ma g n et ica l ly i n d u ce d cr osst a l k. h o w e v e r , sig n if ican t c u r r en t can f l o w t h r o ug h t h e in p u t t e r m ina t io n r e sis t o r s a n d th e lo o p s t h a t dr i v e them. th us , t h e pc b o a r d o n t h e i n p u t side ca n con t r i b u te to ma g n et i c a l ly c o u p l e d c r o sst a l k. f r o m a cir c u i t st a n d p oin t , t h e i n p u t cr osst a l k m e chanism lo oks lik e a c a p a ci t o r co u p lin g t o a r e sis t i v e lo ad . f o r lo w f r e q uen c ies, t h e ma g n i t ude o f t h e cr os s t al k wi l l b e g i v e n b y ( ) [ ] s c r xt m s = 10 log 20 w h er e r s is the s o ur ce r e sis t a n c e , c m is t h e m u t u al c a p a ci t a n c e b e tw e e n t h e t e st sig n a l cir c ui t and t h e s e le c t e d cir c ui t, and s is t h e l a place t r ansfo r m va r i a b le . f r o m th e eq ua t i o n , i t ca n be obse r v ed th a t th i s cr os s t alk m e chanism has a hig h -p ass n a t u r e ; i t can b e m i nimi ze d b y re d u c i ng t h e c o upl i ng c a p a c i t a nc e of t h e i n put c i rc u i t s a n d lo w e r i n g t h e o u t p u t im p e dan c e o f t h e dr i v ers. i f t h e in pu t is dr i v en f r o m a 7 5 ? t e r m ina t e d ca b l e , t h e i n p u t cr os s t al k can b e r e d u ce d b y b u f f er in g t h is sig n a l wi t h a lo w o u t p u t im p e dan c e bu f f e r . on t h e o u t p ut side, t h e cr o sst a l k can b e r e d u ce d b y dr i v in g a lig h t e r lo ad . al t h o u g h t h e ad8 114/ad8115 is s p ecif ie d wi t h exce l l en t dif f er en t i al ga i n an d phas e w h e n dr iv i n g a s t anda r d 150 ? video lo ad , t h e cr os s t al k wil l be hig h er t h a n t h e minim u m ob t a i n a b le d u e t o t h e hig h o u t p u t c u r r en ts. th es e c u r r en ts w i l l i n d u ce cr osst a l k v i a t h e m u t u a l ind u c t an ce o f t h e o u t p u t p i n s and bon d wir e s o f t h e ad8114/ad8115. f r om a c i rc u i t s t an d p o i n t , t h i s output c r o sst a l k me ch a n i s m lo oks li k e a t r ansfo r m e r , wi t h a m u t u a l i n d u c t an ce b e tw e e n t h e windin g s, tha t dr i v es a lo ad r e sis t o r . f o r lo w f r eq uen c ies, t h e ma g n i t u d e o f t h e cr os s t al k is g i ven b y ) / ( log 20 10 l r s mxy xt = w h er e mxy i s t h e m u tu a l i n du c t a n c e of o u tpu t x t o o u t p ut y , a nd r l is t h e lo ad r e sist an ce o n t h e me asur e d ou t p ut. t h is cr osst a l k m e chanism can b e m i nimi ze d b y k e e p in g t h e m u t u a l ind u c t an c e lo w a nd i n cr e a sing r l . th e m u t u al i n d u cta n ce c a n b e k e p t lo w b y i n cr e a sing t h e sp acin g o f t h e cond uc to rs an d mini mi zi n g t h ei r p a ra l l el len g t h .
ad8114/ad8115 rev. b | page 25 of 32 pcb layout e x t r em e ca r e m u s t b e exer cis e d t o mini mi ze addi t i o n al cr os s t al k g e n e ra t e d b y t h e sys t e m cir c ui t bo a r d(s). th e a r e a s t h a t m u st b e ca ref u l l y det a i l e d ar e g r o u n d in g , shie l d ing, sig n a l rou t ing , and sup p ly b y p a ss ing . the p a c k a g in g o f th e ad8114/ad8115 is desig n e d t o he l p k e ep t h e cr osst a l k t o a mi ni m u m. e a ch i n p u t is s e p a ra t e d f r o m e a ch ot he r i n put b y a n an a l o g g r ou n d pi n . a l l of t h e s e a g n d s sh o u l d b e d i r e c t ly co nn e c te d to t h e g r o u nd plane o f t h e c i r c ui t b o a r d . t h e s e g r o u nd p i ns p r o v i d e sh iel d i n g, lo w im p e dan c e r e t u r n p a t h s, and ph ysic al s e p a r a t i o n fo r t h e i n pu ts. al l o f t h es e he l p t o r e d u ce c r os s t al k. e a ch output i s s e p a r a te d f r om it s t w o ne i g hb or i n g output s b y a n an a l o g supply pi n of on e p o l a r i t y or t h e ot he r . e a ch of t h e s e ana l o g su p p ly p i ns p r ov ide s p o we r to t h e ou t p u t st age s of on ly t h e tw o n e a r est o u t p uts. th es e su p p l y p i n s p r o v ide shi e ldi n g, ph y s ica l s e p a ra t i o n , an d a lo w i m p e dan c e su p p ly fo r t h e output s . in d i v i du a l b y p a ss i n g of e a ch of t h e s e s u pply pi ns w i t h a 0.01 f c h i p ca p a ci t o r dir e c t l y t o th e g r o u nd p l a n e minimizes hig h f r e q u e nc y ou t p ut c r o sst a l k v i a t h e me chan is m of shar ing co mm on im p e da n c es. e a c h o u t p u t als o has a n o n -chi p co m p en s a tion ca p a ci t o r tha t is i n d i v i du a l ly t i e d to t h e ne ar b y an a l o g g r ou nd pi ns a g n d 0 0 t h rou g h a g n d 0 7 . t h i s te ch n i q u e re d u c e s c r o sst a l k b y p r e v en t i n g t h e c u r r en ts t h a t f l o w in t h es e p a t h s f r o m s h a r in g a co mm on i m p e da n c e on t h e ic a nd i n t h e p a cka g e p i n s . th e s e a g ndx x sig n a l s sh o u l d a l l b e c o nn e c te d dir e c t ly to t h e g r o u n d pl ane. the i n p u t and ou t p ut sig n a l s wi l l ha ve m i ni m u m cr o sst a l k if t h e y a r e lo ca t e d b e tw e e n g r o u nd plan es o n l a yers a b o v e and b e lo w , an d s e p a r a te d b y g r o u nd in b e tw e e n . v i a s sh o u l d b e lo ca t e d as clos e t o t h e ic as p o ssi b l e t o c a r r y t h e in pu ts and o u t p uts t o t h e i n n e r la yer . th e o n l y place t h e i n p u t and o u t p ut sig n als s u r f ace is a t t h e in p u t t e r m ina t ion r e sis t o r s a n d t h e o u t p u t s e r i es bac k -t er mina tio n r e sis t o r s. th e s e sig n als sh o u ld als o be s e p a ra t e d , t o t h e ext e n t p o s s i b le, as s o on as t h ey em erge fr o m t h e i c p a c k a g e . o p t i m i ze d fo r v i de o a p pli c a t io ns, a l l sig n a l i n p u ts a nd o u t p u t s a r e t e r m ina t e d wi t h 75 ? r e sis t o r s. s t r i plin e t e chniq u es a r e us e d t o achie v e a charac t e r i st ic i m p e dan c e o f 75 ? o n t h e sig n a l in p u t an d o u t p u t lin e s. f i gur e 5 0 s h o w s a cr os s s e c t io n o f on e of t h e i n put or output t r a c k s a l ong w i t h t h e ar r a nge m e n t of t h e p c b l a y e r s . i t s h ou l d b e no te d t h a t u n u s e d re g i ons of t h e f o u r l a y e rs are f i l l e d up w i t h g r ou nd pl ane s . a s a re s u lt , t h e i n put a nd o u tp u t t r ac es, in a d d i t i on to ha v i n g con t r o l l e d im p e dan c es , a r e w e ll s h i e ld e d . 01070-057 w = 0.008" (0.2mm) a = 0.008" (0.2mm) b = 0.0514" (1.3mm) h = 0.025" (0.63mm) t = 0.00135" (0.0343mm) top layer signal layer power layer bottom layer f i g u re 50. cros s s e c t ion of input and o u t p ut t r aces the bo a r d has 3 2 bnc ty p e connec t o rs: 16 in p u ts and 16 ou t p u t s. the co nn e c t o rs a r e a r ra n g e d in a cr es cen t a r o u nd t h e de vice . a s ca n be s e en f r o m f i gur e 53, t h is r e s u l t s in al l 16 in p u t sig n al t r aces a nd al l 16 sig n al o u t p u t t r aces ha vi n g t h e s a m e le n g t h . this is u s e f u l i n te sts su c h as a l l - ho st i l e c r o sst a l k w h e r e t h e p h as e r e l a tio n shi p an d del a y b e tw e e n sig n als n e e d s t o be m a i n ta in e d f r o m in p u t t o o u t p u t . the t h r e e p o w e r s u p p l y p i n s a v c c , d v c c and a v ee sh o u ld b e co nn e c t e d t o g o o d quali t y , lo w n o i s e , 5 v su p p lies. w h er e t h e s a me 5 v p o we r suppl i e s are u s e d for an a l o g and d i g i t a l, sep a ra t e ca b l es s h o u ld be r u n f o r th e p o w e r s u p p l y t o th e e v a l u a t i on b o ard s an a l o g a n d d i g i t a l p o we r supply pi ns . a s a g e n e ral r u le , eac h p o w e r su p p l y p i n (o r gr o u p o f ad j a cen t p o w e r s u p p l y p i n s ) sh o u ld be lo cal l y de co u p le d wi th a 0.01 f ca p a ci t o r . i f t h e r e is a sp ace co nst r a i n t , i t is m o r e im p o r t a n t t o d e c o up l e an a l o g p o we r s u pp l y pi ns b e f o re d i g i t a l p o we r s u pp l y p i n s . a 0.1 f c a p a ci t o r , lo c a t e d r e as o n a b l y c l os e t o t h e p i n s , ca n be us e d t o deco u p le a n u m b er o f p o w e r s u p p l y p i n s . f i nal l y a 10 f ca p a c i t o r s h o u ld be us e d t o deco u p le p o w e r s u p p lies as th ey co m e o n t o th e boa r d .
ad8114/ad8115 rev. b | page 26 of 32 01070-051 f i g u re 51. co mpon ent sid e s ilk s c r e e n 01070-052 f i gur e 5 2 . boar d lay o ut ( c om p o ne nt si de )
ad8114/ad8115 rev. b | page 27 of 32 01070-053 f i g u re 53. bo a r d la yout ( s ig n a l l a yer) 01070-054 f i gure 54. boar d lay o ut ( g r o und plan e)
ad8114/ad8115 rev. b | page 28 of 32 01070-055 f i g u re 55. bo a r d la yout (circuit side) 01070-056 f i gure 56. cir c u i t side silkscreen
ad8114/ad8115 rev. b | page 29 of 32 evaluation board 57,59 58 75 ? input 00 input 00 agnd 75 ? 54 0.01 f 61 60 75 ? input 01 input 01 agnd 63 62 75 ? input 02 input 02 agnd 65 64 75 ? input 03 input 03 agnd 67 66 75 ? input 04 input 04 agnd 69 68 75 ? input 05 input 05 agnd 71 70 75 ? input 06 input 06 agnd 72 75 ? input 07 input 07 5 4 75 ? input 08 input 08 agnd 7 6 75 ? input 09 input 09 agnd 9 8 75 ? input 10 input 10 agnd 11 10 75 ? input 11 input 11 agnd 13 12 75 ? input 12 input 12 agnd 15 14 75 ? input 13 input 13 agnd 17 16 75 ? input 14 input 14 agnd 19 18 75 ? input 15 input 15 agnd 98 data out 96 data in p2-5 p2-4 p2-2 p2-3 p2-1 p2-6 dg nd reset ce cl k /par ser a0 a1 a2 d0 d1 d2 d3 d4 p3 - 1 p3 - 2 p3 - 3 p3 - 4 p3 - 5 p3 - 6 p3 - 7 p3 - 8 p3 - 9 p3 - 1 0 p3 - 1 1 p3 - 1 2 p3 - 1 3 p3 - 1 4 2,74 100 99 97 95 84 83 82 81 80 79 78 77 76 serial mode jump r33 20k ? dvcc output 00 20, 56 avee avee 21, 55 avcc avcc 1, 75 dvcc ad8114/ad8115 dvcc dgnd nc avee agnd avcc nc p1-1 + + + p1-2 p1-3 p1-4 p1-5 p1-6 p1-7 0.1 f1 0 f 0.1 f 0.01 f 0.01 f 0.01 f 10 f 0.1 f1 0 f jumper 3,73 agnd r r r notes r = optional 50 ? terminator resistors c = optional smoothing capacitor r rc r r a3 r r r r r r r r r 94 no connect: 85 ? 9 3 avcc avcc output 00 53 75 ? 52 0.01 f output 01 avee av ee output 01 51 75 ? 50 0.01 f output 02 avcc avcc output 02 49 75 ? 48 0.01 f output 03 avee av ee output 03 47 75 ? 46 0.01 f output 04 avcc avcc output 04 45 75 ? 44 0.01 f output 05 avee av ee output 05 43 75 ? 42 0.01 f output 06 avcc avcc output 06 41 75 ? 40 0.01 f output 07 avee av ee output 07 39 75 ? 38 0.01 f output 08 avcc avcc output 08 37 75 ? 36 0.01 f output 09 avee av ee output 09 35 75 ? 34 0.01 f output 10 avcc avcc output 10 33 75 ? 32 0.01 f output 11 avee av ee output 11 31 75 ? 30 0.01 f output 12 avcc avcc output 12 29 75 ? 28 0.01 f output 13 avee av ee output 13 27 75 ? 26 0.01 f output 14 avcc avcc output 14 25 75 ? 24 0.01 f output 15 avee av ee output 15 23 22 avcc dvcc 01070-050 f i g u re 57. ev aluat i on b o a r d s c h e m a t i c
ad8114/ad8115 rev. b | page 30 of 32 contr o l the evalua tion boar d from a pc clk data in reset update ce dgnd molex 0.100" center crimp terminal housing 1 6 d-sub 25 pin (male) 14 1 25 13 evaluation board pc 2 3 4 5 6 25 3 1 4 5 2 6 signal data in ce reset update clk dgnd molex terminal housing d-sub-25 01070-058 the e v a l ua t i on b o a r d i n cl u d es w i ndo ws?- b a s e d co n t r o l s o f t wa r e and a c u sto m cab l e t h a t co nne c t s t h e b o a r d s dig i t a l i n te r f a c e to t h e pr i n te r p o r t of t h e p c . t h e w i r i ng of t h i s c a bl e is s h o w n in f i g u r e 58. the s o f t wa r e r e q u ir es w i ndo ws 3.1 o r la t e r t o o p era t e . t o in s t al l the s o f t wa r e , in s e r t t h e disk lab e le d dis k 1 o f 2 in t o th e pc an d r u n th e f i le cal l ed s e tup . exe. a d d i t i o n a l inst a l la t i on inst r u c t io n s wi l l b e g i v e n o n - s cr e e n. b e fo r e b e g i n n i n g in st a l l a t i o n , i t is im p o r t an t t o t e r m in a t e an y o t h e r w i ndo ws a p plic a t io n s t h a t a r e r u nning. w h en yo u l a u n ch t h e cr os s p o i n t co n t r o l s o f t w a r e , yo u wi l l b e as k e d t o s e lec t t h e p r in t e r p o r t . m o s t m o der n p c s ha v e onl y o n e p r in t e r p o r t , us ual l y cal l ed lpt1. h o w e v e r s o m e la p t o p co m p u t ers us e t h e prn p o r t . f i g u re 58. ev aluat i on b o a r d- pc co nn ec t i o n cab l e f i g u re 5 9 s h o w s t h e m a i n s c re e n of t h e c o n t ro l s o f t w a re i n it s ini t ial r e s e t sta t e (al l o u t p u t s o f f ) . u s in g t h e mo us e , a n y in p u t ca n be co nn e c t e d wi t h on e o r mo r e o u t p u t s b y s i m p l y c l ic kin g o n t h e a p p r o p r i a t e radio b u t t ons in t h e 16 16 o n -s cr e e n a r ra y . e a ch t i me a b u tton i s cl i c ke d on, t h e s o f t w a re a u tom a t i c a l l y s e nds an d la tches t h e r e quir e d 80-b i t da t a st r e am to t h e eval ua t i o n bo a r d . an o u t p u t can b e t u r n e d o f f b y c l ic kin g t h e a ppropr i a t e butt on i n t h e of f c o lu m n . t o tu r n of f a l l output s , cl ick on res e t . o v ershoot of p c p r in t e r po rt s d a t a lin e s the da t a li n e s on s o m e p r i n t e r p o r t s ha v e exce s s i v e o v ersh o o t. o v ers h o o t o n t h e pin t h a t is us e d as t h e s e r i a l clo c k (p in 6 o n th e d-s u b-25 c o nn ec t o r) ca n c a us e co mm unic a t io n p r ob lem s . this o v ersh o o t ca n b e eli m in a t e d b y co nn e c t i ng a ca p a c i to r f r om t h e c l k l i ne o n t h e e v a l u a t i on b o ard to g r ou nd. a p a d h a s been p r o v i d ed o n t h e ci r c ui t s i d e (c 33) o f t h e ev al ua ti o n b o ard to a l l o w t h i s c a p a c i tor to b e s o l d e r e d i n to pl a c e. d e p e nding o n t h e o v ersh o o t f r o m t h e p r i n t e r p o r t , t h is ca p a ci t o r ma y need t o be as la rge as 0.01 f . w h i l e t h e co m p u t er s o f t wa r e o n l y s u p p o r ts s e r i al p r og ra mmi ng vi a a p c s pa rall e l po r t a n d t h e p r o v i d ed ca b l e , th e eval u a t i o n bo a r d has a co nn ect o r tha t ca n be use d f o r p a ralle l p r o g ra mmin g . the se r / p a r s i gn al s h o u ld be a t a logi c h i gh t o use p a ralle l p r ogra mmin g . th er e is n o cab l e o r so f t wa r e p r o v ided wi th t h e eval ua tio n b o a r d f o r p a ralle l p r ogra mmin g . th e s e a r e lef t t o t h e us er t o p r o v ide . a d 811 4/ a d 8115 p a r a l l e l p or t s e l ect i on 01070- 059 the s o f t wa r e o f fers v o la t i le an d n o n v ola t i l e s t o r a g e o f co nf igura t io n s . f o r v o la t i le st o r a g e , u p t o tw o c o nf igura t io n s ca n b e sto r e d and r e ca l l e d usi n g t h e m e m o r y 1 a nd m e m o r y 2 b u f f ers. th es e f u n c t i on i n a fashio n i d en t i cal to t h e m e m o r y o n a p o cke t c a l c u l ator . f o r non v o l at i l e stor age of a c o n f i g u r a t i o n , t h e s a ve s e t u p and lo ad s e t u p f u n c t i on s can b e us e d . thi s sto r e s t h e co nf igur a t ion as a d a t a f i le on di sk. f i g u r e 5 9 . s c re e n d i s p l a y a n d co n t ro l s o f t w a re
ad8114/ad8115 rev. b | page 31 of 32 outline dimensions compliant to jedec standards ms-026-bed top view (pins down) 1 25 26 51 50 75 76 100 0.50 bsc lead pitch 0.27 0.22 0.17 1.60 max 0.75 0.60 0.45 view a 16.00 bsc sq 14.00 bsc sq pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3. 5 0 f i g u re 60. 1 00-l e a d l o w pr of i l e q u ad f l at p a ck ag e [l qfp] (st - 10 0) di me nsio n sho w n in mi ll im et e r s ordering guide 1 model temperature r a nge package descri ption package option AD8114AST ?40c to +85c 100-lead low prof ile quad flat package [lqfp] st-100 AD8114ASTz 2 ?40c to +85c 100-lead low profile quad flat package [lqfp] st-100 ad8115ast ?40c to +85c 100-lead low prof ile quad flat package [lqfp] st-100 ad8115astz 2 ?40c to +85c 100-lead low profil e quad flat package [lqfp] st-100 ad8114-eval evaluation boar d a d 8 1 1 5 - e v a l e v a l u a t i o n boar d 1 d e t a i ls of t h e l e a d fi n i sh com p osi t i o n ca n be f o un d on t h e ad i web s i t e a t www.analog.com by reviewing the m a terial des c ri ptio n of each r e levant package. 2 z = pb-free part.
ad8114/ad8115 rev. b | page 32 of 32 notes ? 2005 an alog dev i ces, inc. all rights reserve d . t r ad emar ks an d registered tra d emar ks are the prop erty of their respective owners . c01070C0 C 9/05(b)

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